A non volatile memory may be classified into various categories. For example a single poly EEPROM may have a poly silicon layer that may function as a gate and may be formed in a single layer. A stack gate (ETOX) may include two poly silicon layers that may be vertically stacked. A dual poly EEPROM may correspond to an intermediate of a single poly EEPROM and stack gate, a split gate, and the like.
A stack gate may have a smallest cell size and relatively complicated circuits. A stack gate may be suitable for high density and high performance, but may not be suitable for low density. An EEPROM may be used for low density. By way of example, a single poly EEPROM may be manufactured by adding approximately two mask processes during a logic process.
In a single poly type EEPROM, a ratio of a voltage applied to a floating gate to a voltage applied to a select gate may refer to a coupling ratio. As a coupling ratio increases, efficiency of programs may increase. Various methods to improve a coupling ratio have been proposed.
For example, as one method for improving a coupling ratio of a single poly EEPROM, a capacitance region may be doped with an impurity. That is, a bottom of a floating gate may be doped with an N type impurity ion. This method, however, may complicate a manufacturing process of an EEPROM, and a size of a unit cell may not be small. This may result in a problem that an entire size of an EEPROM may increase.